In a high speed communication system, data is often transmitted serially from a transmit station to receiving station through a medium (fiber, coax, etc.) where the receiving station converts the serial data into byte-wide data (for example 8 bits or 10 bits wide). The byte-wide data may be distributed at a back plane data bus to a host computer or to another station which reads in the byte wide data and shifts it out serially to a medium. The byte wide data is distributed at the back plane at a byte rate such that if the bit rate=x bits/s and a byte=y bits, then the byte rate=x/y bits/s.
The back plane data bus is employed to connect at least two back plane circuit boards together and therefore provides the means for point-to-point connection between the back plane boards. Typically, specific boards, such as AT, VME, etc. plug into their corresponding AT, VME, etc. back plane buses.
In a single board design, a high speed bit clock can be divided down to a byte clock. However, to distribute data across multiple back plane circuit boards, it is necessary to send (across the back plane) a high frequency bit clock and a strobe pulse along with the data. The back plan is capacitive in nature and hence, the higher the frequency of the bit clock, the more difficult it is to distribute the bit clock due to the increase in the jitter of the bit clock. In addition, the back plane data bus causes skew mismatch between the bit clock and the strobe pulse which results in adding or dropping bytes from the transmitted data. This invention addresses these issues and provides a clock distribution system and technique for use in a large protocol concentrator in a particular data transmission network: the Fiber Distributed Data Interface (FDDI) network.
The Fiber Distributed Data Interface (FDDI) protocol is an American National Standards Institute (ANSI) data transmission standard which applies to a 100 megabit/second token ring network that utilizes an optical fiber transmission medium. The FDDI protocol is described in "FDDI-an overview," Digests of Papers IEEE Computer Society Int'l Conf., Compcon '87, January, 1987, which is herein incorporated by reference. The FDDI protocol was intended as a high performance interconnection among mainframe computers as well as among mainframes and their associated mass storage sub-systems and other peripheral equipment.
The ANSI, FFDI Physical Layer Medium Dependent, Draft Rev. 9 (Mar. 1, 1989) which describes a multistation network is herein incorporated by reference. Information is transmitted on an FDDI ring in "frames" that consist of a sequence of 5-bit data characters or "symbols." Tokens are used to signify the right to transmit data between stations.
A Physical function (PHY) provides the hardware connection to adjacent stations; it provides the optical fiber hardware components that allow a link from one FDDI station to another. The physical function simultaneously receives and transmits serial data. The physical function's receiver receives the encoded serial data stream from a station through the medium establishes symbol boundaries based on the recognition of a start delimiter symbol pair, and transmits decoded symbols to its associates media access control function (MAC) (FIG. 1).
Referring to FIG. 1 an example of an FDDI data transmission network 10 is illustrated. In FDDI, a communication station 12 is connected optically, via fiber optic medium 14, 16 to a primary ring 14 and a secondary ring 16 which connects the station 12 to a concentrator station 200. The purpose of the secondary ring 16 is for redundancy. Each lettered box A-P, T-Z at a station 12 represents a back plane circuit board. (boards A, B, N in FIGS. 3 and 5). In the illustrated example, there are eleven stations 12, wherein each station 12 has at least one back plane board A-P, T-X. The boards B and W, W and Y, Y and U, U and T, C and T, B and C, O/O and M, L and M, L and O/O, J and S, K and S, J and K, F and I, G and F, G and I, D and E are connected together at the back plane by the back plane bus 20.
A receiving back plane circuit board on the primary ring, (for example board D at Station B receives serial data on the primary ring 14 from another board at another station, for example, from board C at Station 200) converts the serial data it receives from the other board at another station to byte wide data. In FDDI, the serial data rate is 125 MBits/s and the byte wide rate is 12.5 Mbyte/s. The data is transferred from one board (board D for example), to an adjacent board (for example to board E; then from board E to board F: from board F to board G; from board G to board H; from board H to board G; from board G to board I; and from board I to board J, etc.) until the transmitting board Board D receives its own data.
Each board A-P, T-X at each station 12 can optically connect at least one board on another station to it. Hence, all of the stations 12 can be logically connected to the primary FDDI ring 14 via a concentrator 200. In addition, a station 12, or board can be easily bypassed or a station 12 can be easily inserted into the FDDI network 10 via a concentrator 200 thereby eliminating the need for an expensive optical bypass switch.
A scheme that has been employed in the past to distribute byte-wide data across a back plane having a plurality of boards is the first-in-first-out (FIFO) scheme. Each back plane circuit board includes a byte wide FIFO memory or elasticity buffer and its own high frequency bit clock and divided down byte clock. The clock frequency skew between the boards is adjusted by each board's own on-board FIFO memory.
A transmitting station transmits the data and its byte clock to a receiving station which has its own bit and byte clock. The receiving station strobes the transmitted data into its elasticity buffer using the transmitting station's byte clock and, through the use of control circuitry, the data is retrieved by the receiving station's own byte clock for serial transmission. While the FIFO approach allows byte-wide data to be distributed across the back plane, it requires that each back plane board have a costly high frequency crystal oscillator, as well as FIFO memory, and control logic circuitry. Another disadvantage of the FIFO approach is that the FIFO memory delays the data transmission time from board to board.